1. Field of the Invention
The present invention relates to the field of electronics, and in particular to a method for manufacturing a thin-film transistor.
2. The Related Arts
A thin-film transistor (TFT) has been widely used in electronic devices to serve as a switching device and a driving device. Specifically, the thin-film transistors can be formed on a glass substrate or a plastic substrate so that they are commonly used in the field of planar display devices, such as a liquid crystal display (LCD) and an organic light-emitting display (OLED).
Oxide semiconductors have a relatively high electron mobility (the electron mobility of oxide semiconductors >10 cm2/Vs, while the mobility of a-Si being only 0.5-0.8 cm2/Vs) and, compared to low temperature poly-silicon (LTPS), the oxide semiconductors have a simple manufacturing process and has high compatibility with a-Si manufacturing process so as to have a prosperous future of applications and be a hot spot of research of the industry. Among the studies of the oxide semiconductors, InGaZnO (IGZO) semiconductors are the maturest one.
Although having the advantages of having a relatively high electron mobility and a simple manufacturing process, the InGaZnO semiconductors suffer poor stability, being easily affected by temperature and humidity, electrical properties of an InGaZnO semiconductor TFT being shiftable with time, and having severe requirement for conditions of manufacturing process (such as film formation speed, atmosphere of manufacturing process, temperature of manufacturing process, and control of humidity). Further, besides the InGaZnO semiconductor layers themselves, severe requirements are also needed for insulation layers, contact interfaces between the InGaZnO semiconductor layers and the insulation layers, and the contact interfaces between the InGaZnO semiconductor layers and metals.
For a conventional bottom gate coplanar InGaZnO semiconductor, the InGaZnO semiconductor can avoid, after the formation of a source/drain electrode, the damage of the InGaZnO semiconductor layer caused by a manufacturing process of a source/drain terminal of a back channel etching (BCE) TFT. However, in the bottom gate coplanar structure (as shown in FIG. 1), due to a gate insulator (GI) 100 contains defects in itself and the subsequent manufacturing process of a source/drain terminal 300 potentially causing damage to a surface of the GI layer that leads to more defects 500 on the surface of the GI layer 5100, there are more defects 500 existing between an InGaZnO semiconductor layer 700 and the GI layer 100 after the formation of the InGaZnO semiconductor layer 700, imposing a limitation to the mobility of electrons/holes and giving negative influence to the electrical properties of the TFT. Referring to FIG. 2, which shows a plot of an electrical characteristic curve of a conventional bottom gate coplanar TFT, it can be seen from the curve that when a drain voltage Vd=0.1V, the maximum level of a drain current Id is only 10−10 A; and when the drain voltage Vd=10V, the maximum level of the drain current Id is only 10−7 A. The electrical property is thus relatively poor.